//AFE5801
module wrtoadc(
	en,Clkin,data,SCLK,SEN,SDATA
);
input en;//en=1 使能
input Clkin;//20MHz 20ns
input [23:0]data;//addr*8 data*16

output reg SCLK = 0;//10MHz 100ns
output reg SEN = 1;//ADC SPI片选
output reg SDATA = 1'b0;//ADC SPI总线输入

reg [31:0]datalatch;
reg [7:0]s;
reg aa;
reg bb;
reg flag = 0;

always @ (posedge Clkin)//上升沿
	begin
		aa <= en;
		bb <= aa;
	end

always @(posedge Clkin)//生成flag
	begin
		if (aa && !bb)//en上升沿
			flag <= 1;
		else if(s >= 8'h30)
			flag <= 0;
		else
			flag <= flag;
	end

always @(posedge Clkin)//s计数
	begin
		if(flag && !SEN)
			begin
				s <= s+1'h1;
			end
		else if(!flag)
			begin
				s <= 0;
			end
		else
			s <= s;
	end

always@(posedge Clkin)
	begin
		if(!flag)
			begin
				SEN <= 1;
				SCLK <= 0;
				datalatch <= data;
			end
		else
			begin
				SEN <= 0;
				if(!SEN)
					begin
						case(s)
							8'h00: begin SCLK <= 0;SDATA <= datalatch[23]; end
							8'h01: begin SCLK <= 1; end
							8'h02: begin SCLK <= 0;SDATA <= datalatch[22]; end
							8'h03: begin SCLK <= 1; end
							8'h04: begin SCLK <= 0;SDATA <= datalatch[21]; end
							8'h05: begin SCLK <= 1; end
							8'h06: begin SCLK <= 0;SDATA <= datalatch[20]; end
							8'h07: begin SCLK <= 1; end

							8'h08: begin SCLK <= 0;SDATA <= datalatch[19]; end
							8'h09: begin SCLK <= 1; end
							8'h0a: begin SCLK <= 0;SDATA <= datalatch[18]; end
							8'h0b: begin SCLK <= 1; end
							8'h0c: begin SCLK <= 0;SDATA <= datalatch[17]; end
							8'h0d: begin SCLK <= 1; end
							8'h0e: begin SCLK <= 0;SDATA <= datalatch[16]; end
							8'h0f: begin SCLK <= 1; end

							8'h10: begin SCLK <= 0;SDATA <= datalatch[15]; end
							8'h11: begin SCLK <= 1; end
							8'h12: begin SCLK <= 0;SDATA <= datalatch[14]; end
							8'h13: begin SCLK <= 1; end
							8'h14: begin SCLK <= 0;SDATA <= datalatch[13]; end
							8'h15: begin SCLK <= 1; end
							8'h16: begin SCLK <= 0;SDATA <= datalatch[12]; end
							8'h17: begin SCLK <= 1; end

							8'h18: begin SCLK <= 0;SDATA <= datalatch[11]; end
							8'h19: begin SCLK <= 1; end
							8'h1a: begin SCLK <= 0;SDATA <= datalatch[10]; end
							8'h1b: begin SCLK <= 1; end
							8'h1c: begin SCLK <= 0;SDATA <= datalatch[9]; end
							8'h1d: begin SCLK <= 1; end
							8'h1e: begin SCLK <= 0;SDATA <= datalatch[8]; end
							8'h1f: begin SCLK <= 1; end

							8'h20: begin SCLK <= 0;SDATA <= datalatch[7]; end
							8'h21: begin SCLK <= 1; end
							8'h22: begin SCLK <= 0;SDATA <= datalatch[6]; end
							8'h23: begin SCLK <= 1; end
							8'h24: begin SCLK <= 0;SDATA <= datalatch[5]; end
							8'h25: begin SCLK <= 1; end
							8'h26: begin SCLK <= 0;SDATA <= datalatch[4]; end
							8'h27: begin SCLK <= 1; end

							8'h28: begin SCLK <= 0;SDATA <= datalatch[3]; end
							8'h29: begin SCLK <= 1; end
							8'h2a: begin SCLK <= 0;SDATA <= datalatch[2]; end
							8'h2b: begin SCLK <= 1; end
							8'h2c: begin SCLK <= 0;SDATA <= datalatch[1]; end
							8'h2d: begin SCLK <= 1; end
							8'h2e: begin SCLK <= 0;SDATA <= datalatch[0]; end
							8'h2f: begin SCLK <= 1; end

							8'h30: begin SCLK <= 0;SEN <= 1; end

							default: begin SCLK <= SCLK;SDATA <= SDATA; end
						endcase
					end
				else
					begin
						SDATA <= SDATA;
						SCLK <= 0;
					end
			end
	end

endmodule
